Power Efficiency Evaluation of Block Ciphers on GPU-Integrated Multicore Processor

Bibliographic Details
Title:	Power Efficiency Evaluation of Block Ciphers on GPU-Integrated Multicore Processor
Authors:	Nishikawa, Naoki^Aff22, Iwai, Keisuke^Aff22, Kurokawa, Takakazu^Aff22
Contributors:	Hutchison, David, editor^Aff1, Kanade, Takeo, editor^Aff2, Kittler, Josef, editor^Aff3, Kleinberg, Jon M., editor^Aff4, Mattern, Friedemann, editor^Aff5, Mitchell, John C., editor^Aff6, Naor, Moni, editor^Aff7, Nierstrasz, Oscar, editor^Aff8, Pandu Rangan, C., editor^Aff9, Steffen, Bernhard, editor^Aff10, Sudan, Madhu, editor^Aff11, Terzopoulos, Demetri, editor^Aff12, Tygar, Doug, editor^Aff13, Vardi, Moshe Y., editor^Aff14, Weikum, Gerhard, editor^Aff15, Xiang, Yang, editor^Aff16, Stojmenovic, Ivan, editor^Aff17, Apduhan, Bernady O., editor^Aff18, Wang, Guojun, editor^Aff19, Nakano, Koji, editor^Aff20, Zomaya, Albert, editor^Aff21
Source:	Algorithms and Architectures for Parallel Processing : 12th International Conference, ICA3PP 2012, Fukuoka, Japan, September 4-7, 2012, Proceedings, Part I. 7439:347-361
Database:	Springer Nature eBooks

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