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Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS

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Title: Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS
Authors: Rajendra, A.K., Singh Bindra, H., Nauta, B.
Source: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 61(6):2821-2833 Jun, 2026
Database: IEEE Xplore Digital Library
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  Data: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 61(6):2821-2833 Jun, 2026
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        Value: 10.1109/JSSC.2025.3612157
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        StartPage: 2821
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              Type: published
              Y: 2026
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