Rajendra, A., Singh Bindra, H., & Nauta, B. (2026). Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS. IEEE Journal of Solid-State Circuits, Solid-State Circuits, IEEE Journal of, IEEE J. Solid-State Circuits, 61(6), 2821-2833. https://doi.org/10.1109/JSSC.2025.3612157
Παραπομπή σε μορφή Chicago (17η εκδ.)Rajendra, A.K, H. Singh Bindra, και B. Nauta. "Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS." IEEE Journal of Solid-State Circuits, Solid-State Circuits, IEEE Journal of, IEEE J. Solid-State Circuits 61, no. 6 (2026): 2821-2833. https://doi.org/10.1109/JSSC.2025.3612157.
Παραπομπή σε μορφή MLA (9th εκδ.)Rajendra, A.K, et al. "Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS." IEEE Journal of Solid-State Circuits, Solid-State Circuits, IEEE Journal of, IEEE J. Solid-State Circuits, vol. 61, no. 6, 2026, pp. 2821-2833, https://doi.org/10.1109/JSSC.2025.3612157.