Chuang, P., Lorenzelli, F., Wu, C., & Jan Marinissen, E. (2025). Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 44(3), 1155. https://doi.org/10.1109/TCAD.2024.3466809
Παραπομπή σε μορφή Chicago (17η εκδ.)Chuang, P., F. Lorenzelli, C. Wu, και E. Jan Marinissen. "Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 44, no. 3 (2025): 1155. https://doi.org/10.1109/TCAD.2024.3466809.
Παραπομπή σε μορφή MLA (9th εκδ.)Chuang, P., et al. "Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 44, no. 3, 2025, p. 1155, https://doi.org/10.1109/TCAD.2024.3466809.