Λεπτομέρειες βιβλιογραφικής εγγραφής
| Τίτλος: |
A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices |
| Συγγραφείς: |
Swati, Sadhukhan, Ranajoy, Nagar, Mitul S, Engineer, Pinalkumar |
| Πηγή: |
2023 IEEE International Symposium on Smart Electronic Systems (iSES) ISES Smart Electronic Systems (iSES), 2023 IEEE International Symposium on. :409-412 Dec, 2023 |
| Relation: |
2023 IEEE International Symposium on Smart Electronic Systems (iSES) |
| Βάση Δεδομένων: |
IEEE Xplore Digital Library |