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Noble synthesizable hybrid serial-parallel fast multiplier

Bibliographic Details
Title: Noble synthesizable hybrid serial-parallel fast multiplier
Authors: Deogirikar, Abhijit
Publisher Information: Texas A&M University- Kingsville
Publication Year: 2016
Collection: Texas A&M University-Kingsville: AKM Digital Repository
Subject Terms: Electrical engineering, Engineering systems -- Computer simulation, Electrical Engineering -- Testing
Description: The purpose of this study was to synthesize the architecture of a fast multiplier using very highspeed integration circuits hardware description language (VHDL). The serial-parallel architecture proposed by Besher, Bourdine, Ashur and Crookes was synthesized by using Altera ModelSim and Quartus II platform. Low latency, most significant bit (MSB) first (online algebra), signed hybrid multiplier architecture is based on three types of adder cells and has a modular structure. The architecture is easy to expand due to the modular structure. Bit serial and MSB first approach resulted in the architecture’s usefulness for image processing math. Use of the redundant numbering system reduced the carry propagation in the audition process. Timing analysis of the synthesized architecture was performed. 2n-digit product output was achieved at every 2n+3 clock cycles. The synthesized multiplier architecture has an average delay of 1.3 ns.
Document Type: other/unknown material
File Description: pdf
Language: English
Relation: T378.24 D44n; http://cdm16771.contentdm.oclc.org/u?/p16771coll2,114
Availability: http://cdm16771.contentdm.oclc.org/u?/p16771coll2,114
Rights: The right to download or print any of the pages of this thesis (Material) is granted by the copyright owner only for personal or classroom use. The author retains all proprietary rights, including copyright ownership. Any reproduction or editing or other use of this Material by any means requires the express written permission of the copyright owner. Except as provided above, or any use beyond what is allowed by fair use (Title 17 Section 107 U.S.C.), you may not reproduce, republish, post, transmit or distribute any Material from this web site in any physical or digital form without the permission of the copyright owner of the Material. Inquiries regarding any further use of these materials should be addressed to Administration, Jernigan Library, Texas A&M University-Kingsville, 700 University Blvd. Kingsville, Texas 78363-8202, (361)593-3416.
Accession Number: edsbas.9C3553BC
Database: BASE
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  – Url: http://cdm16771.contentdm.oclc.org/u?/p16771coll2,114#
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IllustrationInfo
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  Data: Noble synthesizable hybrid serial-parallel fast multiplier
– Name: Author
  Label: Authors
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  Data: <searchLink fieldCode="AR" term="%22Deogirikar%2C+Abhijit%22">Deogirikar, Abhijit</searchLink>
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  Data: Texas A&M University- Kingsville
– Name: DatePubCY
  Label: Publication Year
  Group: Date
  Data: 2016
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  Data: Texas A&M University-Kingsville: AKM Digital Repository
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  Data: The purpose of this study was to synthesize the architecture of a fast multiplier using very highspeed integration circuits hardware description language (VHDL). The serial-parallel architecture proposed by Besher, Bourdine, Ashur and Crookes was synthesized by using Altera ModelSim and Quartus II platform. Low latency, most significant bit (MSB) first (online algebra), signed hybrid multiplier architecture is based on three types of adder cells and has a modular structure. The architecture is easy to expand due to the modular structure. Bit serial and MSB first approach resulted in the architecture’s usefulness for image processing math. Use of the redundant numbering system reduced the carry propagation in the audition process. Timing analysis of the synthesized architecture was performed. 2n-digit product output was achieved at every 2n+3 clock cycles. The synthesized multiplier architecture has an average delay of 1.3 ns.
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  Data: The right to download or print any of the pages of this thesis (Material) is granted by the copyright owner only for personal or classroom use. The author retains all proprietary rights, including copyright ownership. Any reproduction or editing or other use of this Material by any means requires the express written permission of the copyright owner. Except as provided above, or any use beyond what is allowed by fair use (Title 17 Section 107 U.S.C.), you may not reproduce, republish, post, transmit or distribute any Material from this web site in any physical or digital form without the permission of the copyright owner of the Material. Inquiries regarding any further use of these materials should be addressed to Administration, Jernigan Library, Texas A&M University-Kingsville, 700 University Blvd. Kingsville, Texas 78363-8202, (361)593-3416.
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  Data: edsbas.9C3553BC
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