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Noble synthesizable hybrid serial-parallel fast multiplier

Λεπτομέρειες βιβλιογραφικής εγγραφής
Τίτλος: Noble synthesizable hybrid serial-parallel fast multiplier
Συγγραφείς: Deogirikar, Abhijit
Στοιχεία εκδότη: Texas A&M University- Kingsville
Έτος έκδοσης: 2016
Συλλογή: Texas A&M University-Kingsville: AKM Digital Repository
Θεματικοί όροι: Electrical engineering, Engineering systems -- Computer simulation, Electrical Engineering -- Testing
Περιγραφή: The purpose of this study was to synthesize the architecture of a fast multiplier using very highspeed integration circuits hardware description language (VHDL). The serial-parallel architecture proposed by Besher, Bourdine, Ashur and Crookes was synthesized by using Altera ModelSim and Quartus II platform. Low latency, most significant bit (MSB) first (online algebra), signed hybrid multiplier architecture is based on three types of adder cells and has a modular structure. The architecture is easy to expand due to the modular structure. Bit serial and MSB first approach resulted in the architecture’s usefulness for image processing math. Use of the redundant numbering system reduced the carry propagation in the audition process. Timing analysis of the synthesized architecture was performed. 2n-digit product output was achieved at every 2n+3 clock cycles. The synthesized multiplier architecture has an average delay of 1.3 ns.
Τύπος εγγράφου: other/unknown material
Περιγραφή αρχείου: pdf
Γλώσσα: English
Relation: T378.24 D44n; http://cdm16771.contentdm.oclc.org/u?/p16771coll2,114
Διαθεσιμότητα: http://cdm16771.contentdm.oclc.org/u?/p16771coll2,114
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Αριθμός Καταχώρησης: edsbas.9C3553BC
Βάση Δεδομένων: BASE
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