Dissertation/ Thesis
Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys
| Title: | Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys |
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| Authors: | Araújo, Sílvio Roberto Fernandes de |
| Contributors: | Silva, Ivan Saraiva, http://lattes.cnpq.br/5111916887378777, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2, Susin, Altamiro Amadeu, http://lattes.cnpq.br/6766389440522985, Zeferino, Cesar Albenes, http://lattes.cnpq.br/9888386354516064, Déharbe, David Boris Paul, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4768856U5, Kreutz, Márcio Eduardo, http://lattes.cnpq.br/6374279398246756 |
| Publisher Information: | Universidade Federal do Rio Grande do Norte BR UFRN Programa de Pós-Graduação em Sistemas e Computação Ciência da Computação |
| Publication Year: | 2014 |
| Collection: | Universidade Federal do Rio Grande do Norte: Repositório Institucional (RI UFRN) |
| Subject Terms: | Multiprocessador em chip, MPSoC, Redes em chip, NoC, Algoritmo spiral complement, Sistema IPNoSys, Multiprocessor on chip, Network-on-chip, Spiral complement algorithm, IPNoSys system, CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO |
| Description: | It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it ... |
| Document Type: | doctoral or postdoctoral thesis |
| File Description: | application/pdf |
| Language: | Portuguese |
| Relation: | https://repositorio.ufrn.br/jspui/handle/123456789/17948 |
| Availability: | https://repositorio.ufrn.br/jspui/handle/123456789/17948 |
| Rights: | Acesso Aberto |
| Accession Number: | edsbas.8A9FAF2A |
| Database: | BASE |
| Description not available. |