Academic Journal
Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops
| Τίτλος: | Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops |
|---|---|
| Συγγραφείς: | Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno |
| Συνεισφορές: | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació, Universitat Politècnica de Catalunya. ALBCOM - Algorísmia, Bioinformàtica, Complexitat i Mètodes Formals |
| Πηγή: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) |
| Στοιχεία εκδότη: | Institute of Electrical and Electronics Engineers (IEEE), 2023. |
| Έτος έκδοσης: | 2023 |
| Θεματικοί όροι: | Sequential circuits, Circuits integrats -- Disseny i construcció, Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats, Integrated circuit synthesis, Design automation, Latches, Flip-flops, Integrated circuits -- Design and construction |
| Περιγραφή: | Flip-flops are the most used sequential elements in synchronous circuits, but designs based on latches can operate at higher frequencies and occupy less area. Techniques to increase the maximum operating frequency of flip-flop based designs, such as time-borrowing, rely on tight hold constraints that are difficult to satisfy using traditional back-end optimization techniques. We propose Mix & Latch, a methodology to increase the operating frequency of synchronous digital circuits using a single clock tree and a mixed distribution of positive- and negative-edge-triggered flops, and positive- and negative-level-sensitive latches. An efficient mathematical model is proposed to optimize the type and location of the sequential elements of the circuit. We ensure that the initial registers are not moved from their initial location, although they may change type, thus allowing the use of equivalence checking and static timing analysis to verify formally the correctness of the transformation. The technique is validated using a 28nm CMOS FDSOI technology, obtaining 1.33X post-layout average operating frequency improvement on a broad set of benchmarks over a standard commercial design flow. Additionally, the circuit area was also reduced by more than 1.19X on average for the same benchmarks, although the overall area reduction is not a goal of the optimization algorithm. To the best of our knowledge, this is the first work that proposes combining mixed-polarity flip-flops and latches to improve the circuit performance. |
| Τύπος εγγράφου: | Article |
| Περιγραφή αρχείου: | application/pdf |
| ISSN: | 2169-3536 |
| DOI: | 10.1109/access.2023.3265809 |
| Σύνδεσμος πρόσβασης: | https://ieeexplore.ieee.org/document/10097737 https://doi.org/10.1109/ACCESS.2023.3265809 https://hdl.handle.net/11583/2977854 https://hdl.handle.net/2117/387551 https://doi.org/10.1109/access.2023.3265809 |
| Rights: | CC BY NC ND |
| Αριθμός Καταχώρησης: | edsair.doi.dedup.....26f44a91b237f28d1b94f3e82694eec2 |
| Βάση Δεδομένων: | OpenAIRE |
| ISSN: | 21693536 |
|---|---|
| DOI: | 10.1109/access.2023.3265809 |