Λεπτομέρειες βιβλιογραφικής εγγραφής
| Τίτλος: |
Address Translation for Throughput-Oriented Accelerators. |
| Συγγραφείς: |
Pichai, Bharath1, Hsu, Lisa2, Bhattacharjee, Abhishek1 |
| Πηγή: |
IEEE Micro. May2015, Vol. 35 Issue 3, p102-113. 12p. |
| Θεματικοί όροι: |
*Computer programming management, *Algorithms, *Virtual storage (Computer science), *Computer storage devices, Central processing units, Graphics processing units |
| Περίληψη: |
The proliferation of heterogeneous computing platforms necessitates a manageable programming model to ensure widespread adoption. A key component of this is a shared unified address space between the heterogeneous units to obtain virtual memory's programmability benefits. To this end, the authors explore how to design memory management units (MMUs), critical hardware support for unified address spaces, on heterogeneous systems (namely, CPUs and GPUs). This article sets the foundation for reasoning about GPU MMUs and shows how they must be carefully codesigned with warp schedulers and the overall memory hierarchy. [ABSTRACT FROM PUBLISHER] |
|
Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) |
| Βάση Δεδομένων: |
Business Source Index |