Λεπτομέρειες βιβλιογραφικής εγγραφής
| Τίτλος: |
一种面向嵌入式场景的五级流水线 RISC-V 处理器设计. |
| Alternate Title: |
Design of five-stage pipelined RISC-V processor for embedded scenarios. |
| Συγγραφείς: |
于安宁1,2, 黄 晗1,2, 利 节1,2, 曾孝平3 |
| Πηγή: |
Application Research of Computers / Jisuanji Yingyong Yanjiu. Sep2026, Vol. 43 Issue 9, p2767-2772. 6p. |
| Θεματικοί όροι: |
*Microprocessor design & construction, *Embedded computer systems, *Internet of things, *Verilog (Computer hardware description language) |
| Abstract (English): |
To meet the demands of distributed control nodes in intelligent connected vehicles and Internet of Things (IoT) applications for low cost, low power consumption, and high real-time performance, this paper designed and implemented a 32 bit five-stage pipelined processor core based on the RISC-V RV32IM instruction set. The processor adopted a five-stage pipeline architecture and integrated a hardware multiply-divide unit. It introduced dynamic branch prediction and data forwarding techniques to suppress pipeline stalls caused by control hazards and data hazards, thus improving instruction execution efficiency per unit frequency. It implemented the processor in Verilog HDL and constructed a system-on-chip (SoC) over the AXI4-Lite bus. Differential testing completed the logical functional verification. Comprehensive evaluation on the Xilinx KU5P FPGA platform shows that the processor consumes only 5 712 Slice LUTs and 2 091 registers at 200 MHz. It achieves 1. 62 DMIPS / MHz and 2. 81 CoreMark / MHz. Compared with hummingbird E203, DMIPS and CoreMark performance improve by 30. 6% and 31. 3%, respectively. Compared with VexRiscv, the improvements reach 30. 6% and 19. 6%, respectively. Results demonstrate that this architecture maintains an extremely low hardware resource footprint while significantly enhancing computational efficiency. It provides a RISC-V processor solution that balances high performance and high energy efficiency for resource-constrained embedded applications. [ABSTRACT FROM AUTHOR] |
| Abstract (Chinese): |
针对智能网联汽车与物联网领域分布式控制节点对低成本、低功耗及高实时性的需求, 设计并实现了 一款基于 RISC- V RV32IM 指令集的 32 位五级流水线处理器核。 处理器采用五级流水结构, 集成硬件乘除法单 元, 引入动态分支预测与数据前递技术, 有效抑制了控制冒险与数据冒险导致的流水线停顿, 提高了单位频率下 的指令执行效率。 处理器采用 Verilog HDL 实现, 基于 AXI4-Lite 总线构建片上系统 (SoC), 并通过差分测试完成 逻辑功能验证。 在 Xilinx KU5P FPGA 平台上的综合测试结果表明: 在 200 MHz 工作频率下, 该处理器仅消耗 5 712 个 Slice LUT 和 2 091 个寄存器, 性能表现达到 1. 62 DMIPS/MHz 与 2. 81 CoreMark/MHz。 与蜂鸟 E203 相 比, DMIPS 和 CoreMark 性能分别提升 30. 6% 和 31. 3% ;与 VexRiscv 相比分别提升 30. 6% 和 19. 6%。 该架构在 维持极低硬件资源消耗的同时, 显著提升了运算效能, 为资源受限的嵌入式应用提供了一种兼顾高性能与高能 效的 RISC- V 处理器解决方案 [ABSTRACT FROM AUTHOR] |
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