Bibliographic Details
| Title: |
A comprehensive review on implementation analysis of 5-Stage pipelined RISC-V processor. |
| Authors: |
Vaishnavi, C. M.1 (AUTHOR) vaishnavicm03@gmail.com, Trupti, R.1 (AUTHOR) trupti11ravi04@gmail.com, Asuti, Manjunath G.1 (AUTHOR) manjunathasuti@bnmit.in, Munavalli, Jyoti R.1 (AUTHOR) jyotirmunavalli@bnmit.in |
| Source: |
AIP Conference Proceedings. 2026, Vol. 3426 Issue 1, p1-6. 6p. |
| Subject Terms: |
*Microprocessor design & construction, *Reduced instruction set computers |
| Abstract: |
The evolution of Reduced Instruction Set Computing (RISC) architectures has been a significant factor in modern processor design. RISC-V, an open-source ISA, has gained widespread adoption due to its modularity and efficiency. This paper presents a comprehensive review of the 5-stage pipelined RISC-V processor, covering its architecture, performance optimizations, implementation techniques, and comparative analysis with other processor architectures. The study in depth discusses issues such as hazard detection, forwarding mechanisms, and branch prediction necessary for high pipelined performance. In addition, several variations of the processor are analyzed along with their feasibility and practical relevance. [ABSTRACT FROM AUTHOR] |
| Database: |
Academic Search Index |