Λεπτομέρειες βιβλιογραφικής εγγραφής
| Τίτλος: |
Investigation of P-I-N Forward Leakage in Tunnel FETs: A Simulation Study. |
| Συγγραφείς: |
Haneef, Nazia1 (AUTHOR) naziahaneef370@gmail.com, Yasir Bashir, Md2 (AUTHOR), Adil Raushan, Mohd3 (AUTHOR), Siddiqui, Mohammad Jawaid1 (AUTHOR) |
| Πηγή: |
IETE Journal of Research. May2026, p1-12. 12p. 24 Illustrations. |
| Θεματικοί όροι: |
*Tunnel field-effect transistors, *Electric currents, *Digital electronics, *Computers, *Computer simulation |
| Περίληψη: |
Recent advancements in AI and ML algorithms demand high-density and low-power devices. The Tunnel Field-Effect Transistor (TFET) presents a viable strategy for digital systems with reduced power consumption. The overall performance of digital circuits that use TFETs is deteriorated by the substantial P-I-N forward leakage currents that these devices encounter when exposed to large negative drain-to-source voltages. Therefore, using 2-D simulations, we discuss in detail the nature of P-I-N forward leakage current dependency on the negative drain voltages. In addition, we have analyzed how basic device design parameters affect the P-I-N forward leakage current. Furthermore, a novel TFET structure having an additional electrode has been proposed to mitigate the P-I-N forward leakage current. The suggested architecture is an attractive substitute for conventional TFETs since it substantially decreases ambipolar current by three orders of magnitude and forward leakage current by ten orders of magnitude. [ABSTRACT FROM AUTHOR] |
| Βάση Δεδομένων: |
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