Constraining designs for syntheis and timing analysis : a practical guide to synopsys design constraints (SDC)
Αποθηκεύτηκε σε:
| Κύριοι συγγραφείς: | , |
|---|---|
| Μορφή: | Βιβλίο |
| Γλώσσα: | English |
| Δημοσίευση: |
New York :
Springer,
c2013.
|
| Θέματα: | |
| Ετικέτες: |
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|---|---|---|---|
| 001 | 1/112058 | ||
| 008 | 160923t2013####nyu| ||| |||| ||eng|| | ||
| 020 | |a 9781461432685 | ||
| 040 | |a GR-MyUa |b gre |c GR-MyUa |e AACR2 | ||
| 041 | 0 | |a eng | |
| 082 | 7 | |a 621.3815 |2 (23) | |
| 100 | 1 | |a Gangadharan, Sridhar. | |
| 245 | 1 | 0 | |a Constraining designs for syntheis and timing analysis : |b a practical guide to synopsys design constraints (SDC) / |c Sridhar Gangadharan, Sanjay Churiwala ; with Chapter 17 contributed by Frederic Revenu. |
| 260 | |a New York : |b Springer, |c c2013. | ||
| 300 | |a xxvii, 226 σ. : |b σχέδια ; |c 25 εκ. | ||
| 504 | |a Βιβλιογραφία: σ. 219. Ευρετήριο. | ||
| 650 | 0 | |a Timing circuits. | |
| 650 | 0 | |a Integrated circuits |x Design and construction. | |
| 650 | 0 | |a Real-time clocks (Computers) | |
| 650 | 0 | |a Constraint programming (Computer science) | |
| 650 | 0 | |a Systems on a chip |x Design. | |
| 700 | 1 | |a Churiwala, Sanjay, |e aut | |
| 700 | 1 | |a Revenu, Frederic, |e oth | |
| 852 | |a INST |b SAMOS |e 20160923 |h 621.3815 GAN |p 005300043811 |q 005300043811 |t BK |y 0 | ||
| 922 | |a 3ΕΛΗ |b 201607 |c ΤΜΠΕΣ |d Δρές | ||
| 970 | |a Κοσιέρης |b Χρήστος |z 23-09-2016 | ||