Mangiras, D., Chinnery, D., & Dimitrakopoulos, G. (2023). Task-Based Parallel Programming for Gate Sizing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 42(4), 1309. https://doi.org/10.1109/TCAD.2022.3197490
Παραπομπή σε μορφή Chicago (17η εκδ.)Mangiras, D., D. Chinnery, και G. Dimitrakopoulos. "Task-Based Parallel Programming for Gate Sizing." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 42, no. 4 (2023): 1309. https://doi.org/10.1109/TCAD.2022.3197490.
Παραπομπή σε μορφή MLA (9th εκδ.)Mangiras, D., et al. "Task-Based Parallel Programming for Gate Sizing." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 42, no. 4, 2023, p. 1309, https://doi.org/10.1109/TCAD.2022.3197490.