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Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access

Bibliographic Details
Title: Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access
Authors: S, Kavitha, S, Harini, P, Kaviya, S, Kanishka
Source: 2026 International Conference on Secure Information Systems and Technologies (ICSIST) Secure Information Systems and Technologies (ICSIST), 2026 International Conference on. :177-183 Aug, 2026
Relation: 2026 International Conference on Secure Information Systems and Technologies (ICSIST)
Database: IEEE Xplore Digital Library
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  Availability: 0
Header DbId: edseee
DbLabel: IEEE Xplore Digital Library
An: edseee.11706328
RelevancyScore: 1178
AccessLevel: 2
PubType: Conference
PubTypeId: conference
PreciseRelevancyScore: 1177.97497558594
IllustrationInfo
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  Data: Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access
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  Data: 2026 International Conference on Secure Information Systems and Technologies (ICSIST) Secure Information Systems and Technologies (ICSIST), 2026 International Conference on. :177-183 Aug, 2026
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RecordInfo BibRecord:
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      – Type: doi
        Value: 10.1109/ICSIST70215.2026.11706328
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        PageCount: 7
        StartPage: 177
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      – TitleFull: Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access
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            NameFull: S, Kavitha
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            NameFull: S, Harini
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            NameFull: P, Kaviya
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            NameFull: S, Kanishka
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          Dates:
            – D: 17
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              Type: published
              Y: 2026
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