Conference
Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access
| Title: | Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access |
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| Authors: | S, Kavitha, S, Harini, P, Kaviya, S, Kanishka |
| Source: | 2026 International Conference on Secure Information Systems and Technologies (ICSIST) Secure Information Systems and Technologies (ICSIST), 2026 International Conference on. :177-183 Aug, 2026 |
| Relation: | 2026 International Conference on Secure Information Systems and Technologies (ICSIST) |
| Database: | IEEE Xplore Digital Library |
| ISBN: | 9798331583897 9798331583880 9798331583903 |
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| DOI: | 10.1109/ICSIST70215.2026.11706328 |