S, K., S, H., P, K., & S, K. (2026). Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access. 2026 International Conference on Secure Information Systems and Technologies (ICSIST), Secure Information Systems and Technologies (ICSIST), 2026 International Conference on, 177. https://doi.org/10.1109/ICSIST70215.2026.11706328
Παραπομπή σε μορφή Chicago (17η εκδ.)S, Kavitha, Harini S, Kaviya P, και Kanishka S. "Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access." 2026 International Conference on Secure Information Systems and Technologies (ICSIST), Secure Information Systems and Technologies (ICSIST), 2026 International Conference on 2026: 177. https://doi.org/10.1109/ICSIST70215.2026.11706328.
Παραπομπή σε μορφή MLA (9th εκδ.)S, Kavitha, et al. "Design and Verilog Implementation of a Byte-Enabled RAM Architecture for Efficient Data Access." 2026 International Conference on Secure Information Systems and Technologies (ICSIST), Secure Information Systems and Technologies (ICSIST), 2026 International Conference on, 2026, p. 177, https://doi.org/10.1109/ICSIST70215.2026.11706328.