Conference
View in EDS

A Hardware-Efficient Dual-Mode Polynomial Sampling Architecture with Hash Integration for Post-Quantum Cryptography

Bibliographic Details
Title: A Hardware-Efficient Dual-Mode Polynomial Sampling Architecture with Hash Integration for Post-Quantum Cryptography
Authors: Sravya, Alahari Sri Lakshmi, Venkatapavani, Basu, Islam, MD Najrul
Source: 2026 30th International Symposium on VLSI Design and Test (VDAT) VLSI Design and Test (VDAT), 2026 30th International Symposium on. :7-11 Aug, 2026
Relation: 2026 30th International Symposium on VLSI Design and Test (VDAT)
Database: IEEE Xplore Digital Library
FullText Text:
  Availability: 0
Header DbId: edseee
DbLabel: IEEE Xplore Digital Library
An: edseee.11704630
RelevancyScore: 1178
AccessLevel: 2
PubType: Conference
PubTypeId: conference
PreciseRelevancyScore: 1177.97534179688
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: A Hardware-Efficient Dual-Mode Polynomial Sampling Architecture with Hash Integration for Post-Quantum Cryptography
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Sravya%2C+Alahari+Sri+Lakshmi%22">Sravya, Alahari Sri Lakshmi</searchLink><br /><searchLink fieldCode="AR" term="%22Venkatapavani%2C+Basu%22">Venkatapavani, Basu</searchLink><br /><searchLink fieldCode="AR" term="%22Islam%2C+MD+Najrul%22">Islam, MD Najrul</searchLink>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: 2026 30th International Symposium on VLSI Design and Test (VDAT) VLSI Design and Test (VDAT), 2026 30th International Symposium on. :7-11 Aug, 2026
– Name: NoteTitleSource
  Label: Relation
  Group: SrcInfo
  Data: 2026 30th International Symposium on VLSI Design and Test (VDAT)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edseee&AN=edseee.11704630
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/VDAT72243.2026.11704630
    PhysicalDescription:
      Pagination:
        PageCount: 5
        StartPage: 7
    Titles:
      – TitleFull: A Hardware-Efficient Dual-Mode Polynomial Sampling Architecture with Hash Integration for Post-Quantum Cryptography
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Sravya, Alahari Sri Lakshmi
      – PersonEntity:
          Name:
            NameFull: Venkatapavani, Basu
      – PersonEntity:
          Name:
            NameFull: Islam, MD Najrul
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 20
              M: 08
              Type: published
              Y: 2026
          Identifiers:
            – Type: isbn-print
              Value: 9798319524782
            – Type: isbn-print
              Value: 9798319524799
            – Type: issn-locals
              Value: edseee.IEEEConferenc
          Titles:
            – TitleFull: 2026 30th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2026 30th International Symposium on
              Type: main
ResultId 1