APA (7th ed.) Citation

Sravya, A. S. L., Venkatapavani, B., & Islam, M. N. (2026). A Hardware-Efficient Dual-Mode Polynomial Sampling Architecture with Hash Integration for Post-Quantum Cryptography. 2026 30th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2026 30th International Symposium on, 7. https://doi.org/10.1109/VDAT72243.2026.11704630

Chicago Style (17th ed.) Citation

Sravya, Alahari Sri Lakshmi, Basu Venkatapavani, and MD Najrul Islam. "A Hardware-Efficient Dual-Mode Polynomial Sampling Architecture with Hash Integration for Post-Quantum Cryptography." 2026 30th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2026 30th International Symposium on 2026: 7. https://doi.org/10.1109/VDAT72243.2026.11704630.

MLA (9th ed.) Citation

Sravya, Alahari Sri Lakshmi, et al. "A Hardware-Efficient Dual-Mode Polynomial Sampling Architecture with Hash Integration for Post-Quantum Cryptography." 2026 30th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2026 30th International Symposium on, 2026, p. 7, https://doi.org/10.1109/VDAT72243.2026.11704630.