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CVL-SIMD: A Lightweight Hybrid Simd/Vector Execution Architecture for Edge-Oriented RISC-V Processors

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Τίτλος: CVL-SIMD: A Lightweight Hybrid Simd/Vector Execution Architecture for Edge-Oriented RISC-V Processors
Συγγραφείς: Anoop, R., Vishvakarma, Santosh Kumar
Πηγή: 2026 30th International Symposium on VLSI Design and Test (VDAT) VLSI Design and Test (VDAT), 2026 30th International Symposium on. :388-393 Aug, 2026
Relation: 2026 30th International Symposium on VLSI Design and Test (VDAT)
Βάση Δεδομένων: IEEE Xplore Digital Library
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  Availability: 0
Header DbId: edseee
DbLabel: IEEE Xplore Digital Library
An: edseee.11704614
RelevancyScore: 1178
AccessLevel: 2
PubType: Conference
PubTypeId: conference
PreciseRelevancyScore: 1177.97534179688
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: CVL-SIMD: A Lightweight Hybrid Simd/Vector Execution Architecture for Edge-Oriented RISC-V Processors
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Anoop%2C+R%2E%22">Anoop, R.</searchLink><br /><searchLink fieldCode="AR" term="%22Vishvakarma%2C+Santosh+Kumar%22">Vishvakarma, Santosh Kumar</searchLink>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: 2026 30th International Symposium on VLSI Design and Test (VDAT) VLSI Design and Test (VDAT), 2026 30th International Symposium on. :388-393 Aug, 2026
– Name: NoteTitleSource
  Label: Relation
  Group: SrcInfo
  Data: 2026 30th International Symposium on VLSI Design and Test (VDAT)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edseee&AN=edseee.11704614
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/VDAT72243.2026.11704614
    PhysicalDescription:
      Pagination:
        PageCount: 6
        StartPage: 388
    Titles:
      – TitleFull: CVL-SIMD: A Lightweight Hybrid Simd/Vector Execution Architecture for Edge-Oriented RISC-V Processors
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Anoop, R.
      – PersonEntity:
          Name:
            NameFull: Vishvakarma, Santosh Kumar
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 20
              M: 08
              Type: published
              Y: 2026
          Identifiers:
            – Type: isbn-print
              Value: 9798319524782
            – Type: isbn-print
              Value: 9798319524799
            – Type: issn-locals
              Value: edseee.IEEEConferenc
          Titles:
            – TitleFull: 2026 30th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2026 30th International Symposium on
              Type: main
ResultId 1