Anoop, R., & Vishvakarma, S. K. (2026). CVL-SIMD: A Lightweight Hybrid Simd/Vector Execution Architecture for Edge-Oriented RISC-V Processors. 2026 30th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2026 30th International Symposium on, 388. https://doi.org/10.1109/VDAT72243.2026.11704614
Παραπομπή σε μορφή Chicago (17η εκδ.)Anoop, R., και Santosh Kumar Vishvakarma. "CVL-SIMD: A Lightweight Hybrid Simd/Vector Execution Architecture for Edge-Oriented RISC-V Processors." 2026 30th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2026 30th International Symposium on 2026: 388. https://doi.org/10.1109/VDAT72243.2026.11704614.
Παραπομπή σε μορφή MLA (9th εκδ.)Anoop, R., και Santosh Kumar Vishvakarma. "CVL-SIMD: A Lightweight Hybrid Simd/Vector Execution Architecture for Edge-Oriented RISC-V Processors." 2026 30th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2026 30th International Symposium on, 2026, p. 388, https://doi.org/10.1109/VDAT72243.2026.11704614.