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An Area-Efficient CNN Accelerator for Handwritten Digit Recognition on FPGA-Based Edge Systems

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Τίτλος: An Area-Efficient CNN Accelerator for Handwritten Digit Recognition on FPGA-Based Edge Systems
Συγγραφείς: K, Aiswarya, Francis, Bibin, G, Lakshminarayanan, Gopi, Varun P
Πηγή: 2026 30th International Symposium on VLSI Design and Test (VDAT) VLSI Design and Test (VDAT), 2026 30th International Symposium on. :350-355 Aug, 2026
Relation: 2026 30th International Symposium on VLSI Design and Test (VDAT)
Βάση Δεδομένων: IEEE Xplore Digital Library
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        Value: 10.1109/VDAT72243.2026.11704603
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        PageCount: 6
        StartPage: 350
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      – TitleFull: An Area-Efficient CNN Accelerator for Handwritten Digit Recognition on FPGA-Based Edge Systems
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            NameFull: K, Aiswarya
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            NameFull: Francis, Bibin
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            NameFull: G, Lakshminarayanan
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            NameFull: Gopi, Varun P
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              Type: published
              Y: 2026
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