FPGA-Based Hardware Accelerator for U-Net: A Resource-Efficient, Pipelined Micro-Architecture for Real-Time Image Segmentation

Λεπτομέρειες βιβλιογραφικής εγγραφής
Τίτλος: FPGA-Based Hardware Accelerator for U-Net: A Resource-Efficient, Pipelined Micro-Architecture for Real-Time Image Segmentation
Συγγραφείς: Karunanayake, K. O. Y. N., Deshapriya, H. D. I. J. A., Saiamirthan, A. T., Pathirana, P. M. C. N. V., Ekanayake, K. U., Gamage, T. D.
Πηγή: 2026 Moratuwa Engineering Research Conference (MERCon) Moratuwa Engineering Research Conference (MERCon), 2026. :628-633 Aug, 2026
Relation: 2026 Moratuwa Engineering Research Conference (MERCon)
Βάση Δεδομένων: IEEE Xplore Digital Library