APA (7th ed.) Citation

Karunanayake, K. O. Y. N., Deshapriya, H. D. I. J. A., Saiamirthan, A. T., Pathirana, P. M. C. N. V., Ekanayake, K. U., & Gamage, T. D. (2026). FPGA-Based Hardware Accelerator for U-Net: A Resource-Efficient, Pipelined Micro-Architecture for Real-Time Image Segmentation. 2026 Moratuwa Engineering Research Conference (MERCon), Moratuwa Engineering Research Conference (MERCon), 2026, 628. https://doi.org/10.1109/MERCon71835.2026.11691407

Chicago Style (17th ed.) Citation

Karunanayake, K. O. Y. N., H. D. I. J. A. Deshapriya, A. T. Saiamirthan, P. M. C. N. V. Pathirana, K. U. Ekanayake, and T. D. Gamage. "FPGA-Based Hardware Accelerator for U-Net: A Resource-Efficient, Pipelined Micro-Architecture for Real-Time Image Segmentation." 2026 Moratuwa Engineering Research Conference (MERCon), Moratuwa Engineering Research Conference (MERCon), 2026 2026: 628. https://doi.org/10.1109/MERCon71835.2026.11691407.

MLA (9th ed.) Citation

Karunanayake, K. O. Y. N., et al. "FPGA-Based Hardware Accelerator for U-Net: A Resource-Efficient, Pipelined Micro-Architecture for Real-Time Image Segmentation." 2026 Moratuwa Engineering Research Conference (MERCon), Moratuwa Engineering Research Conference (MERCon), 2026, 2026, p. 628, https://doi.org/10.1109/MERCon71835.2026.11691407.