Conference
A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications
| Τίτλος: | A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications |
|---|---|
| Συγγραφείς: | Nagabushanam, P, Umasree, Nayani, Subramanyam, Radha, K, Vasanth, Kiranmaie, P, Kumar, P. Venkatesh |
| Πηγή: | 2026 7th International Conference on Electronics and Sustainable Communication Systems (ICESC) Electronics and Sustainable Communication Systems (ICESC), 2026 7th International Conference on. :841-846 Aug, 2026 |
| Relation: | 2026 7th International Conference on Electronics and Sustainable Communication Systems (ICESC) |
| Βάση Δεδομένων: | IEEE Xplore Digital Library |
καταχωρήστε σχόλιο πρώτοι!