Conference
A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications
| Title: | A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications |
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| Authors: | Nagabushanam, P, Umasree, Nayani, Subramanyam, Radha, K, Vasanth, Kiranmaie, P, Kumar, P. Venkatesh |
| Source: | 2026 7th International Conference on Electronics and Sustainable Communication Systems (ICESC) Electronics and Sustainable Communication Systems (ICESC), 2026 7th International Conference on. :841-846 Aug, 2026 |
| Relation: | 2026 7th International Conference on Electronics and Sustainable Communication Systems (ICESC) |
| Database: | IEEE Xplore Digital Library |
| ISBN: | 9798331562717 9798331562700 9798331562724 |
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| ISSN: | 29965357 29965349 |
| DOI: | 10.1109/ICESC70182.2026.11687277 |