Nagabushanam, P., Umasree, N., Subramanyam, R., K, V., Kiranmaie, P., & Kumar, P. V. (2026). A Power-Aware 64-bit Hybrid Multiplier using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications. 2026 7th International Conference on Electronics and Sustainable Communication Systems (ICESC), Electronics and Sustainable Communication Systems (ICESC), 2026 7th International Conference on, 841. https://doi.org/10.1109/ICESC70182.2026.11687277
Παραπομπή σε μορφή Chicago (17η εκδ.)Nagabushanam, P., Nayani Umasree, Radha Subramanyam, Vasanth K, P. Kiranmaie, και P. Venkatesh Kumar. "A Power-Aware 64-bit Hybrid Multiplier Using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications." 2026 7th International Conference on Electronics and Sustainable Communication Systems (ICESC), Electronics and Sustainable Communication Systems (ICESC), 2026 7th International Conference on 2026: 841. https://doi.org/10.1109/ICESC70182.2026.11687277.
Παραπομπή σε μορφή MLA (9th εκδ.)Nagabushanam, P., et al. "A Power-Aware 64-bit Hybrid Multiplier Using Vedic Arithmetic and Wallace Tree for High-Performance Filter Applications." 2026 7th International Conference on Electronics and Sustainable Communication Systems (ICESC), Electronics and Sustainable Communication Systems (ICESC), 2026 7th International Conference on, 2026, p. 841, https://doi.org/10.1109/ICESC70182.2026.11687277.