Academic Journal
SpikeEdge: A Residual Spiking Neural Network Architecture With Edge-Based Data Encoding for Efficient Hardware Design
| Τίτλος: | SpikeEdge: A Residual Spiking Neural Network Architecture With Edge-Based Data Encoding for Efficient Hardware Design |
|---|---|
| Συγγραφείς: | Mishra, S.M., Kundu, S., Meitei, N.Y., Shekhawat, H.S., Trivedi, G. |
| Πηγή: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 34(10):3288-3298 Oct, 2026 |
| Βάση Δεδομένων: | IEEE Xplore Digital Library |
| FullText | Links: – Type: other Text: Availability: 0 |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2026.3718287 PhysicalDescription: Pagination: PageCount: 11 StartPage: 3288 Titles: – TitleFull: SpikeEdge: A Residual Spiking Neural Network Architecture With Edge-Based Data Encoding for Efficient Hardware Design Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Mishra, S.M. – PersonEntity: Name: NameFull: Kundu, S. – PersonEntity: Name: NameFull: Meitei, N.Y. – PersonEntity: Name: NameFull: Shekhawat, H.S. – PersonEntity: Name: NameFull: Trivedi, G. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 10638210 – Type: issn-print Value: 15579999 – Type: issn-locals Value: edseee.IEEEJournals Numbering: – Type: volume Value: 34 – Type: issue Value: 10 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst. Type: main |
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