Mishra, S., Kundu, S., Meitei, N., Shekhawat, H., & Trivedi, G. (2026). SpikeEdge: A Residual Spiking Neural Network Architecture With Edge-Based Data Encoding for Efficient Hardware Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst., 34(10), 3288. https://doi.org/10.1109/TVLSI.2026.3718287
Παραπομπή σε μορφή Chicago (17η εκδ.)Mishra, S.M, S. Kundu, N.Y Meitei, H.S Shekhawat, και G. Trivedi. "SpikeEdge: A Residual Spiking Neural Network Architecture With Edge-Based Data Encoding for Efficient Hardware Design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst. 34, no. 10 (2026): 3288. https://doi.org/10.1109/TVLSI.2026.3718287.
Παραπομπή σε μορφή MLA (9th εκδ.)Mishra, S.M, et al. "SpikeEdge: A Residual Spiking Neural Network Architecture With Edge-Based Data Encoding for Efficient Hardware Design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst., vol. 34, no. 10, 2026, p. 3288, https://doi.org/10.1109/TVLSI.2026.3718287.