Zhao, Z., Lai, N., & Sha, J. (2026). High-Throughput LDPC Decoder for nand Flash: Turbo Two-Bit Gradient Descent Bit-Flipping Algorithm and VLSI Architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst., 34(10), 3243. https://doi.org/10.1109/TVLSI.2026.3717043
Παραπομπή σε μορφή Chicago (17η εκδ.)Zhao, Z., N. Lai, και J. Sha. "High-Throughput LDPC Decoder for Nand Flash: Turbo Two-Bit Gradient Descent Bit-Flipping Algorithm and VLSI Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst. 34, no. 10 (2026): 3243. https://doi.org/10.1109/TVLSI.2026.3717043.
Παραπομπή σε μορφή MLA (9th εκδ.)Zhao, Z., et al. "High-Throughput LDPC Decoder for Nand Flash: Turbo Two-Bit Gradient Descent Bit-Flipping Algorithm and VLSI Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst., vol. 34, no. 10, 2026, p. 3243, https://doi.org/10.1109/TVLSI.2026.3717043.