Kersz, I., Ely, A., Jordan, M., Azambuja, J., Kastensmidt, F., & Beck, A. (2026). HEADS: Accuracy--Makespan Co-Optimization for Multitenant Multi-FPGA Edge Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst., 34(10), 3116. https://doi.org/10.1109/TVLSI.2026.3716149
Παραπομπή σε μορφή Chicago (17η εκδ.)Kersz, I., A.F Ely, M.G Jordan, J.R Azambuja, F.L Kastensmidt, και A.C.S Beck. "HEADS: Accuracy--Makespan Co-Optimization for Multitenant Multi-FPGA Edge Systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst. 34, no. 10 (2026): 3116. https://doi.org/10.1109/TVLSI.2026.3716149.
Παραπομπή σε μορφή MLA (9th εκδ.)Kersz, I., et al. "HEADS: Accuracy--Makespan Co-Optimization for Multitenant Multi-FPGA Edge Systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst., vol. 34, no. 10, 2026, p. 3116, https://doi.org/10.1109/TVLSI.2026.3716149.