Palani, R., Srivastava, A., Barola, R., & Saha, K. (2026). Architecture and Design of 1.6-GS/s Digital Frequency Up/Down Converter Based on Polyphase Filter Bank. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst., 34(10), 3212. https://doi.org/10.1109/TVLSI.2026.3715920
Παραπομπή σε μορφή Chicago (17η εκδ.)Palani, R.K, A. Srivastava, R. Barola, και K. Saha. "Architecture and Design of 1.6-GS/s Digital Frequency Up/Down Converter Based on Polyphase Filter Bank." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst. 34, no. 10 (2026): 3212. https://doi.org/10.1109/TVLSI.2026.3715920.
Παραπομπή σε μορφή MLA (9th εκδ.)Palani, R.K, et al. "Architecture and Design of 1.6-GS/s Digital Frequency Up/Down Converter Based on Polyphase Filter Bank." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, IEEE Trans. VLSI Syst., vol. 34, no. 10, 2026, p. 3212, https://doi.org/10.1109/TVLSI.2026.3715920.