Conference
Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration
| Title: | Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration |
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| Authors: | V, Lavanya, M, Madeliene Jennilia, M A, Muthiah, N, Mathan |
| Source: | 2026 6th International Conference on Intelligent Technologies (CONIT) Intelligent Technologies (CONIT), 2026 6th International Conference on. :1-7 Jun, 2026 |
| Relation: | 2026 6th International Conference on Intelligent Technologies (CONIT) |
| Database: | IEEE Xplore Digital Library |
| ISBN: | 9798319518569 9798319518583 9798319518590 |
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| DOI: | 10.1109/CONIT69683.2026.11620705 |