Conference
Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration
| Τίτλος: | Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration |
|---|---|
| Συγγραφείς: | V, Lavanya, M, Madeliene Jennilia, M A, Muthiah, N, Mathan |
| Πηγή: | 2026 6th International Conference on Intelligent Technologies (CONIT) Intelligent Technologies (CONIT), 2026 6th International Conference on. :1-7 Jun, 2026 |
| Relation: | 2026 6th International Conference on Intelligent Technologies (CONIT) |
| Βάση Δεδομένων: | IEEE Xplore Digital Library |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: edseee DbLabel: IEEE Xplore Digital Library An: edseee.11620705 RelevancyScore: 1161 AccessLevel: 2 PubType: Conference PubTypeId: conference PreciseRelevancyScore: 1160.62585449219 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22V%2C+Lavanya%22">V, Lavanya</searchLink><br /><searchLink fieldCode="AR" term="%22M%2C+Madeliene+Jennilia%22">M, Madeliene Jennilia</searchLink><br /><searchLink fieldCode="AR" term="%22M+A%2C+Muthiah%22">M A, Muthiah</searchLink><br /><searchLink fieldCode="AR" term="%22N%2C+Mathan%22">N, Mathan</searchLink> – Name: TitleSource Label: Source Group: Src Data: 2026 6th International Conference on Intelligent Technologies (CONIT) Intelligent Technologies (CONIT), 2026 6th International Conference on. :1-7 Jun, 2026 – Name: NoteTitleSource Label: Relation Group: SrcInfo Data: 2026 6th International Conference on Intelligent Technologies (CONIT) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edseee&AN=edseee.11620705 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/CONIT69683.2026.11620705 PhysicalDescription: Pagination: PageCount: 7 StartPage: 1 Titles: – TitleFull: Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: V, Lavanya – PersonEntity: Name: NameFull: M, Madeliene Jennilia – PersonEntity: Name: NameFull: M A, Muthiah – PersonEntity: Name: NameFull: N, Mathan IsPartOfRelationships: – BibEntity: Dates: – D: 19 M: 06 Type: published Y: 2026 Identifiers: – Type: isbn-print Value: 9798319518569 – Type: isbn-print Value: 9798319518583 – Type: isbn-print Value: 9798319518590 – Type: issn-locals Value: edseee.IEEEConferenc Titles: – TitleFull: 2026 6th International Conference on Intelligent Technologies (CONIT), Intelligent Technologies (CONIT), 2026 6th International Conference on Type: main |
| ResultId | 1 |