V, L., M, M. J., M A, M., & N, M. (2026). Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration. 2026 6th International Conference on Intelligent Technologies (CONIT), Intelligent Technologies (CONIT), 2026 6th International Conference on, 1. https://doi.org/10.1109/CONIT69683.2026.11620705
Παραπομπή σε μορφή Chicago (17η εκδ.)V, Lavanya, Madeliene Jennilia M, Muthiah M A, και Mathan N. "Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration." 2026 6th International Conference on Intelligent Technologies (CONIT), Intelligent Technologies (CONIT), 2026 6th International Conference on 2026: 1. https://doi.org/10.1109/CONIT69683.2026.11620705.
Παραπομπή σε μορφή MLA (9th εκδ.)V, Lavanya, et al. "Design and Implementation of a 32-bit RISC-V Processor with Sparse MAC, Accumulator, and Activation Support for AI Acceleration." 2026 6th International Conference on Intelligent Technologies (CONIT), Intelligent Technologies (CONIT), 2026 6th International Conference on, 2026, p. 1, https://doi.org/10.1109/CONIT69683.2026.11620705.