APA (7th ed.) Citation

Li, Z., Han, C., Xiao, Q., Wang, W., Zhang, Y., Zhou, J., & Zhao, B. (2026). An Area-Efficient Neural Stimulator Chip Achieving 23V Voltage Compliance by 180nm BCD CMOS process. 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Circuits and Systems (ISCAS), 2026 IEEE International Symposium on, 3421. https://doi.org/10.1109/ISCAS66217.2026.11562486

Chicago Style (17th ed.) Citation

Li, Zherui, Cheng Han, Qijing Xiao, Weixiao Wang, Yunshan Zhang, Jun Zhou, and Bo Zhao. "An Area-Efficient Neural Stimulator Chip Achieving 23V Voltage Compliance by 180nm BCD CMOS Process." 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Circuits and Systems (ISCAS), 2026 IEEE International Symposium on 2026: 3421. https://doi.org/10.1109/ISCAS66217.2026.11562486.

MLA (9th ed.) Citation

Li, Zherui, et al. "An Area-Efficient Neural Stimulator Chip Achieving 23V Voltage Compliance by 180nm BCD CMOS Process." 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Circuits and Systems (ISCAS), 2026 IEEE International Symposium on, 2026, p. 3421, https://doi.org/10.1109/ISCAS66217.2026.11562486.