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A Novel Latch Reset Technique Enabling Sub- $6 \mu ~\mathrm{W}$ Operation in Double-Tail Comparator

Bibliographic Details
Title: A Novel Latch Reset Technique Enabling Sub- $6 \mu ~\mathrm{W}$ Operation in Double-Tail Comparator
Authors: Dubey, Aditya, Rathore, Sunil, Bagga, Navjeet
Source: 2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID) VLSID VLSI Design & 25th International Conference on Embedded Systems (VLSID), 2026 39th International Conference on. :443-448 Jan, 2026
Relation: 2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID)
Database: IEEE Xplore Digital Library
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PubType: Conference
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      – Type: doi
        Value: 10.1109/VLSID68508.2026.00089
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        PageCount: 6
        StartPage: 443
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      – TitleFull: A Novel Latch Reset Technique Enabling Sub- $6 \mu ~\mathrm{W}$ Operation in Double-Tail Comparator
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            NameFull: Dubey, Aditya
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            NameFull: Rathore, Sunil
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            NameFull: Bagga, Navjeet
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            – D: 03
              M: 01
              Type: published
              Y: 2026
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