Dubey, A., Rathore, S., & Bagga, N. (2026). A Novel Latch Reset Technique Enabling Sub- $6 \mu ~\mathrm{W}$ Operation in Double-Tail Comparator. 2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID), VLSI Design & 25th International Conference on Embedded Systems (VLSID), 2026 39th International Conference on, VLSID, 443. https://doi.org/10.1109/VLSID68508.2026.00089
Παραπομπή σε μορφή Chicago (17η εκδ.)Dubey, Aditya, Sunil Rathore, και Navjeet Bagga. "A Novel Latch Reset Technique Enabling Sub- $6 \mu ~\mathrm{W}$ Operation in Double-Tail Comparator." 2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID), VLSI Design & 25th International Conference on Embedded Systems (VLSID), 2026 39th International Conference on, VLSID 2026: 443. https://doi.org/10.1109/VLSID68508.2026.00089.
Παραπομπή σε μορφή MLA (9th εκδ.)Dubey, Aditya, et al. "A Novel Latch Reset Technique Enabling Sub- $6 \mu ~\mathrm{W}$ Operation in Double-Tail Comparator." 2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID), VLSI Design & 25th International Conference on Embedded Systems (VLSID), 2026 39th International Conference on, VLSID, 2026, p. 443, https://doi.org/10.1109/VLSID68508.2026.00089.