Academic Journal
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip
| Τίτλος: | A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip |
|---|---|
| Συγγραφείς: | Dong, Z., Li, S., Zhu, W., Li, A., Wang, Q., Jing, N., Sheng, W., Jiang, J., Mao, Z. |
| Πηγή: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 33(6):1502-1515 Jun, 2025 |
| Βάση Δεδομένων: | IEEE Xplore Digital Library |
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