APA (7th ed.) Citation

Zhang, W., Luo, Y., Zhang, Y., Ouyang, J., Wang, G., Wang, X., . . . An, F. (2024). A 43.3 bit/cycle Inflate Accelerator Featuring Static-Dynamic Huffman Decoder with Multiple Checkpoints and Optimized End-Of-Block Control for Hyperscale data. 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), Solid-State Circuits Conference (A-SSCC), 2024 IEEE Asian, 1. https://doi.org/10.1109/A-SSCC60305.2024.10848802

Chicago Style (17th ed.) Citation

Zhang, Wei, Yiwei Luo, Yangyi Zhang, Jiaqi Ouyang, Guodong Wang, Xianglong Wang, Gang Shi, Lei Chen, and Fengwei An. "A 43.3 Bit/cycle Inflate Accelerator Featuring Static-Dynamic Huffman Decoder with Multiple Checkpoints and Optimized End-Of-Block Control for Hyperscale Data." 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), Solid-State Circuits Conference (A-SSCC), 2024 IEEE Asian 2024: 1. https://doi.org/10.1109/A-SSCC60305.2024.10848802.

MLA (9th ed.) Citation

Zhang, Wei, et al. "A 43.3 Bit/cycle Inflate Accelerator Featuring Static-Dynamic Huffman Decoder with Multiple Checkpoints and Optimized End-Of-Block Control for Hyperscale Data." 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), Solid-State Circuits Conference (A-SSCC), 2024 IEEE Asian, 2024, p. 1, https://doi.org/10.1109/A-SSCC60305.2024.10848802.