Kolagatla, V. R., Raveendran, A., & Desalphine, V. (2024). Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing. 2024 28th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2024 28th International Symposium on, 1. https://doi.org/10.1109/VDAT63601.2024.10705670
Παραπομπή σε μορφή Chicago (17η εκδ.)Kolagatla, Venkata Reddy, Aneesh Raveendran, και Vivian Desalphine. "Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing." 2024 28th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2024 28th International Symposium on 2024: 1. https://doi.org/10.1109/VDAT63601.2024.10705670.
Παραπομπή σε μορφή MLA (9th εκδ.)Kolagatla, Venkata Reddy, et al. "Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing." 2024 28th International Symposium on VLSI Design and Test (VDAT), VLSI Design and Test (VDAT), 2024 28th International Symposium on, 2024, p. 1, https://doi.org/10.1109/VDAT63601.2024.10705670.