VHDL Modeling for Digital Design Synthesis

Bibliographic Details
Title:	VHDL Modeling for Digital Design Synthesis
Description:	The purpose of this book is to introduce VHSIC Hardware Description Lan guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im plementationtechnolo~y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs.
Authors:	Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
Resource Type:	eBook.
Subjects:	Digital electronics--Computer simulation, VHDL (Computer hardware description language), Computer aided design
Categories:	COMPUTERS / Computer Science, COMPUTERS / Design, Graphics & Media / CAD-CAM, TECHNOLOGY & ENGINEERING / General, TECHNOLOGY & ENGINEERING / Electrical, TECHNOLOGY & ENGINEERING / Electronics / Circuits / General
Database:	eBook Index

FullText	Text: Availability: 0
Header	DbId: edsebk DbLabel: eBook Index An: 2854809 RelevancyScore: 592 AccessLevel: 6 PubType: eBook PubTypeId: ebook PreciseRelevancyScore: 591.781860351563
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Items	– Name: Title Label: Title Group: Ti Data: VHDL Modeling for Digital Design Synthesis – Name: Abstract Label: Description Group: Ab Data: The purpose of this book is to introduce VHSIC Hardware Description Lan guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im plementationtechnolo~y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Yu-Chin+Hsu%22">Yu-Chin Hsu</searchLink><br /><searchLink fieldCode="AR" term="%22Kevin+F%2E+Tsai%22">Kevin F. Tsai</searchLink><br /><searchLink fieldCode="AR" term="%22Jessie+T%2E+Liu%22">Jessie T. Liu</searchLink><br /><searchLink fieldCode="AR" term="%22Eric+S%2E+Lin%22">Eric S. Lin</searchLink> – Name: TypePub Label: Resource Type Group: TypPub Data: eBook. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Digital+electronics--Computer+simulation%22">Digital electronics--Computer simulation</searchLink><br /><searchLink fieldCode="DE" term="%22VHDL+%28Computer+hardware+description+language%29%22">VHDL (Computer hardware description language)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+aided+design%22">Computer aided design</searchLink> – Name: SubjectBISAC Label: Categories Group: Su Data: <searchLink fieldCode="ZK" term="%22COMPUTERS+%2F+Computer+Science%22">COMPUTERS / Computer Science</searchLink><br /><searchLink fieldCode="ZK" term="%22COMPUTERS+%2F+Design%2C+Graphics+%26+Media+%2F+CAD-CAM%22">COMPUTERS / Design, Graphics & Media / CAD-CAM</searchLink><br /><searchLink fieldCode="ZK" term="%22TECHNOLOGY+%26+ENGINEERING+%2F+General%22">TECHNOLOGY & ENGINEERING / General</searchLink><br /><searchLink fieldCode="ZK" term="%22TECHNOLOGY+%26+ENGINEERING+%2F+Electrical%22">TECHNOLOGY & ENGINEERING / Electrical</searchLink><br /><searchLink fieldCode="ZK" term="%22TECHNOLOGY+%26+ENGINEERING+%2F+Electronics+%2F+Circuits+%2F+General%22">TECHNOLOGY & ENGINEERING / Electronics / Circuits / General</searchLink>
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RecordInfo	BibRecord: BibEntity: Classifications: – Code: 004.0151 Scheme: ddc Type: prePub Languages: – Code: eng Text: English Subjects: – SubjectFull: Digital electronics--Computer simulation Type: general – SubjectFull: VHDL (Computer hardware description language) Type: general – SubjectFull: Computer aided design Type: general Titles: – TitleFull: VHDL Modeling for Digital Design Synthesis Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Yu-Chin Hsu – PersonEntity: Name: NameFull: Kevin F. Tsai – PersonEntity: Name: NameFull: Jessie T. Liu – PersonEntity: Name: NameFull: Eric S. Lin – PersonEntity: Name: NameFull: Yu-Chin Hsu – PersonEntity: Name: NameFull: Kevin F. Tsai – PersonEntity: Name: NameFull: Jessie T. Liu – PersonEntity: Name: NameFull: Eric S. Lin IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Type: published Y: 1995 – D: 16 M: 04 Type: profile Y: 2021 Identifiers: – Type: isbn-print Value: 9780792395973 – Type: isbn-print Value: 9781461359937 – Type: isbn-electronic Value: 9781461523437 Titles: – TitleFull: VHDL Modeling for Digital Design Synthesis Type: main
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