eBook
Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers
| Τίτλος: | Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers |
|---|---|
| Περιγραφή: | This book provides a comprehensive discussion of UML/OCL methods and design flow, for automatic validation and verification of hardware and software systems. While the presented flow focuses on using satisfiability solvers, the authors also describe how these methods can be used for any other automatic reasoning engine. Additionally, the design flow described is applied to a broad variety of validation and verification tasks. The authors also cover briefly how non-functional properties such as timing constraints can be handled with the described flow. |
| Συγγραφείς: | Nils Przigoda, Robert Wille, Judith Przigoda, Rolf Drechsler |
| Resource Type: | eBook. |
| Θέματα: | Computer programs--Validation, Computer programs--Verification, Electronics, Computer software--Verification, Object-oriented methods (Computer science), UML (Computer science), Computer software--Validation, Systems engineering |
| Categories: | TECHNOLOGY & ENGINEERING / Electronics / Circuits / General, COMPUTERS / Computer Architecture, TECHNOLOGY & ENGINEERING / Electronics / General |
| Βάση Δεδομένων: | eBook Index |
| FullText | Text: Availability: 0 |
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| Header | DbId: edsebk DbLabel: eBook Index An: 1693236 RelevancyScore: 937 AccessLevel: 6 PubType: eBook PubTypeId: ebook PreciseRelevancyScore: 937.174743652344 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers – Name: Abstract Label: Description Group: Ab Data: This book provides a comprehensive discussion of UML/OCL methods and design flow, for automatic validation and verification of hardware and software systems. While the presented flow focuses on using satisfiability solvers, the authors also describe how these methods can be used for any other automatic reasoning engine. Additionally, the design flow described is applied to a broad variety of validation and verification tasks. The authors also cover briefly how non-functional properties such as timing constraints can be handled with the described flow. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Nils+Przigoda%22">Nils Przigoda</searchLink><br /><searchLink fieldCode="AR" term="%22Robert+Wille%22">Robert Wille</searchLink><br /><searchLink fieldCode="AR" term="%22Judith+Przigoda%22">Judith Przigoda</searchLink><br /><searchLink fieldCode="AR" term="%22Rolf+Drechsler%22">Rolf Drechsler</searchLink> – Name: TypePub Label: Resource Type Group: TypPub Data: eBook. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+programs--Validation%22">Computer programs--Validation</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+programs--Verification%22">Computer programs--Verification</searchLink><br /><searchLink fieldCode="DE" term="%22Electronics%22">Electronics</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software--Verification%22">Computer software--Verification</searchLink><br /><searchLink fieldCode="DE" term="%22Object-oriented+methods+%28Computer+science%29%22">Object-oriented methods (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22UML+%28Computer+science%29%22">UML (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software--Validation%22">Computer software--Validation</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+engineering%22">Systems engineering</searchLink> – Name: SubjectBISAC Label: Categories Group: Su Data: <searchLink fieldCode="ZK" term="%22TECHNOLOGY+%26+ENGINEERING+%2F+Electronics+%2F+Circuits+%2F+General%22">TECHNOLOGY & ENGINEERING / Electronics / Circuits / General</searchLink><br /><searchLink fieldCode="ZK" term="%22COMPUTERS+%2F+Computer+Architecture%22">COMPUTERS / Computer Architecture</searchLink><br /><searchLink fieldCode="ZK" term="%22TECHNOLOGY+%26+ENGINEERING+%2F+Electronics+%2F+General%22">TECHNOLOGY & ENGINEERING / Electronics / General</searchLink> |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edsebk&AN=1693236 |
| RecordInfo | BibRecord: BibEntity: Classifications: – Code: 005.117 Scheme: ddc Type: prePub Languages: – Code: eng Text: English Subjects: – SubjectFull: Computer programs--Validation Type: general – SubjectFull: Computer programs--Verification Type: general – SubjectFull: Electronics Type: general – SubjectFull: Computer software--Verification Type: general – SubjectFull: Object-oriented methods (Computer science) Type: general – SubjectFull: UML (Computer science) Type: general – SubjectFull: Computer software--Validation Type: general – SubjectFull: Systems engineering Type: general Titles: – TitleFull: Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Nils Przigoda – PersonEntity: Name: NameFull: Robert Wille – PersonEntity: Name: NameFull: Judith Przigoda – PersonEntity: Name: NameFull: Rolf Drechsler – PersonEntity: Name: NameFull: Nils Przigoda – PersonEntity: Name: NameFull: Robert Wille – PersonEntity: Name: NameFull: Judith Przigoda – PersonEntity: Name: NameFull: Rolf Drechsler IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Type: published Y: 2018 – D: 26 M: 01 Type: profile Y: 2018 Identifiers: – Type: isbn-print Value: 9783319728131 – Type: isbn-electronic Value: 9783319728148 Titles: – TitleFull: Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers Type: main |
| ResultId | 1 |