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An FPGA Implementation of Stochastic Computing-Based LSTM

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Title: An FPGA Implementation of Stochastic Computing-Based LSTM
Authors: Maor, Guy A
Contributors: Hu, Yang
Publication Year: 2019
Subject Terms: Computer engineering--Data processing, Internet of things, Energy consumption, Field programmable gate arrays
Description: As a special type of recurrent neural networks (RNN), Long Short Term Memory (LSTM) is capable of processing sequential data with a great improvement in accuracy, and is widely applied in image/video recognition and speech recognition. However, LSTM typically possesses high computational complexity and may cause high hardware cost and power consumption when being implemented. With the development of Internet of Things (IoT) and mobile/edge computation, lots of mobile and edge devices with limited resources are widely deployed, which further exacerbates the situation. Recently, Stochastic Computing (SC) has been applied into neural networks (NN) (e.g., convolution neural networks, CNN) structure to improve the power efficiency. Essentially, SC can effectively simplify the fundamental arithmetic circuits (e.g., multiplication), and reduce the hardware cost and power consumption. Therefore, this thesis introduces SC into LSTM and creatively proposes an SC-based LSTM architecture design to save the hardware cost and power consumption. More importantly, the thesis successfully implements the design on an Field Programmable Gate Array (FPGA) and evaluates its performance on the MNIST dataset. The evaluation results show that the SC-LSTM design works smoothly and can significantly reduce power consumption by 73.24% compared to the baseline binary LSTM implementation without much accuracy loss. In the future, SC can potentially save hardware cost and reduce power consumption in a wide range of IoT and mobile/edge applications.
Document Type: thesis
File Description: application/pdf
Language: English
Relation: https://hdl.handle.net/10735.1/7197
Availability: https://hdl.handle.net/10735.1/7197
Rights: ©2019 Guy A. Maor. All Rights Reserved.
Accession Number: edsbas.E445DAE7
Database: BASE
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IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: An FPGA Implementation of Stochastic Computing-Based LSTM
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Maor%2C+Guy+A%22">Maor, Guy A</searchLink>
– Name: Author
  Label: Contributors
  Group: Au
  Data: Hu, Yang
– Name: DatePubCY
  Label: Publication Year
  Group: Date
  Data: 2019
– Name: Subject
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  Data: <searchLink fieldCode="DE" term="%22Computer+engineering--Data+processing%22">Computer engineering--Data processing</searchLink><br /><searchLink fieldCode="DE" term="%22Internet+of+things%22">Internet of things</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink>
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  Label: Description
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  Data: As a special type of recurrent neural networks (RNN), Long Short Term Memory (LSTM) is capable of processing sequential data with a great improvement in accuracy, and is widely applied in image/video recognition and speech recognition. However, LSTM typically possesses high computational complexity and may cause high hardware cost and power consumption when being implemented. With the development of Internet of Things (IoT) and mobile/edge computation, lots of mobile and edge devices with limited resources are widely deployed, which further exacerbates the situation. Recently, Stochastic Computing (SC) has been applied into neural networks (NN) (e.g., convolution neural networks, CNN) structure to improve the power efficiency. Essentially, SC can effectively simplify the fundamental arithmetic circuits (e.g., multiplication), and reduce the hardware cost and power consumption. Therefore, this thesis introduces SC into LSTM and creatively proposes an SC-based LSTM architecture design to save the hardware cost and power consumption. More importantly, the thesis successfully implements the design on an Field Programmable Gate Array (FPGA) and evaluates its performance on the MNIST dataset. The evaluation results show that the SC-LSTM design works smoothly and can significantly reduce power consumption by 73.24% compared to the baseline binary LSTM implementation without much accuracy loss. In the future, SC can potentially save hardware cost and reduce power consumption in a wide range of IoT and mobile/edge applications.
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      – Text: English
    Subjects:
      – SubjectFull: Computer engineering--Data processing
        Type: general
      – SubjectFull: Internet of things
        Type: general
      – SubjectFull: Energy consumption
        Type: general
      – SubjectFull: Field programmable gate arrays
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      – TitleFull: An FPGA Implementation of Stochastic Computing-Based LSTM
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            NameFull: Hu, Yang
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              Y: 2019
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