Dissertation/ Thesis
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Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys ; The study of viability of development of no processor integrated system based on network-on-chip: IPNoSys system

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Τίτλος: Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys ; The study of viability of development of no processor integrated system based on network-on-chip: IPNoSys system
Συγγραφείς: Araújo, Sílvio Roberto Fernandes de
Συνεισφορές: Silva, Ivan Saraiva, http://lattes.cnpq.br/5111916887378777, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2, Sousa, Fernando Rangel de, http://lattes.cnpq.br/9092018794878372, Netto, Eduardo Bráulio Wanderley, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4798543Y3, Bampi, Sérgio, http://lattes.cnpq.br/4010781324120944
Στοιχεία εκδότη: Universidade Federal do Rio Grande do Norte
BR
UFRN
Programa de Pós-Graduação em Sistemas e Computação
Ciência da Computação
Έτος έκδοσης: 2014
Συλλογή: Universidade Federal do Rio Grande do Norte: Repositório Institucional (RI UFRN)
Θεματικοί όροι: Sistema em chip (SoC), Redes em chip (NoC), Algoritmo spiral complement, Sistema IPNoSys, System-on-chip (SoC), Network-on-chip (NoC), Spiral complement algorithm, IPNoSys system, CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
Περιγραφή: The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The ...
Τύπος εγγράφου: master thesis
Περιγραφή αρχείου: application/pdf
Γλώσσα: Portuguese
Relation: https://repositorio.ufrn.br/jspui/handle/123456789/17969
Διαθεσιμότητα: https://repositorio.ufrn.br/jspui/handle/123456789/17969
Rights: Acesso Aberto
Αριθμός Καταχώρησης: edsbas.CFAEFD3E
Βάση Δεδομένων: BASE
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  Data: Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys ; The study of viability of development of no processor integrated system based on network-on-chip: IPNoSys system
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  Data: Silva, Ivan Saraiva<br />http://lattes.cnpq.br/5111916887378777<br />http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2<br />Sousa, Fernando Rangel de<br />http://lattes.cnpq.br/9092018794878372<br />Netto, Eduardo Bráulio Wanderley<br />http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4798543Y3<br />Bampi, Sérgio<br />http://lattes.cnpq.br/4010781324120944
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  Data: Universidade Federal do Rio Grande do Norte<br />BR<br />UFRN<br />Programa de Pós-Graduação em Sistemas e Computação<br />Ciência da Computação
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  Data: 2014
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  Data: Universidade Federal do Rio Grande do Norte: Repositório Institucional (RI UFRN)
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  Data: <searchLink fieldCode="DE" term="%22Sistema+em+chip+%28SoC%29%22">Sistema em chip (SoC)</searchLink><br /><searchLink fieldCode="DE" term="%22Redes+em+chip+%28NoC%29%22">Redes em chip (NoC)</searchLink><br /><searchLink fieldCode="DE" term="%22Algoritmo+spiral+complement%22">Algoritmo spiral complement</searchLink><br /><searchLink fieldCode="DE" term="%22Sistema+IPNoSys%22">Sistema IPNoSys</searchLink><br /><searchLink fieldCode="DE" term="%22System-on-chip+%28SoC%29%22">System-on-chip (SoC)</searchLink><br /><searchLink fieldCode="DE" term="%22Network-on-chip+%28NoC%29%22">Network-on-chip (NoC)</searchLink><br /><searchLink fieldCode="DE" term="%22Spiral+complement+algorithm%22">Spiral complement algorithm</searchLink><br /><searchLink fieldCode="DE" term="%22IPNoSys+system%22">IPNoSys system</searchLink><br /><searchLink fieldCode="DE" term="%22CNPQ%3A%3ACIENCIAS+EXATAS+E+DA+TERRA%3A%3ACIENCIA+DA+COMPUTACAO%3A%3ASISTEMAS+DE+COMPUTACAO%22">CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO</searchLink>
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  Group: Ab
  Data: The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The ...
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      – Text: Portuguese
    Subjects:
      – SubjectFull: Sistema em chip (SoC)
        Type: general
      – SubjectFull: Redes em chip (NoC)
        Type: general
      – SubjectFull: Algoritmo spiral complement
        Type: general
      – SubjectFull: Sistema IPNoSys
        Type: general
      – SubjectFull: System-on-chip (SoC)
        Type: general
      – SubjectFull: Network-on-chip (NoC)
        Type: general
      – SubjectFull: Spiral complement algorithm
        Type: general
      – SubjectFull: IPNoSys system
        Type: general
      – SubjectFull: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
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