Dissertation/ Thesis
Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys ; The study of viability of development of no processor integrated system based on network-on-chip: IPNoSys system
| Title: | Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys ; The study of viability of development of no processor integrated system based on network-on-chip: IPNoSys system |
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| Authors: | Araújo, Sílvio Roberto Fernandes de |
| Contributors: | Silva, Ivan Saraiva, http://lattes.cnpq.br/5111916887378777, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2, Sousa, Fernando Rangel de, http://lattes.cnpq.br/9092018794878372, Netto, Eduardo Bráulio Wanderley, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4798543Y3, Bampi, Sérgio, http://lattes.cnpq.br/4010781324120944 |
| Publisher Information: | Universidade Federal do Rio Grande do Norte BR UFRN Programa de Pós-Graduação em Sistemas e Computação Ciência da Computação |
| Publication Year: | 2014 |
| Collection: | Universidade Federal do Rio Grande do Norte: Repositório Institucional (RI UFRN) |
| Subject Terms: | Sistema em chip (SoC), Redes em chip (NoC), Algoritmo spiral complement, Sistema IPNoSys, System-on-chip (SoC), Network-on-chip (NoC), Spiral complement algorithm, IPNoSys system, CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO |
| Description: | The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The ... |
| Document Type: | master thesis |
| File Description: | application/pdf |
| Language: | Portuguese |
| Relation: | https://repositorio.ufrn.br/jspui/handle/123456789/17969 |
| Availability: | https://repositorio.ufrn.br/jspui/handle/123456789/17969 |
| Rights: | Acesso Aberto |
| Accession Number: | edsbas.CFAEFD3E |
| Database: | BASE |
| Description not available. |