Conference
View in EDS

PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning

Bibliographic Details
Title: PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning
Authors: Nadalini D., Rusci M., Tagliavini G., Ravaglia L., Benini L., Conti F.
Contributors: Nadalini D., Rusci M., Tagliavini G., Ravaglia L., Benini L., Conti F.
Publisher Information: Springer
Publication Year: 2022
Collection: IRIS Università degli Studi di Bologna (CRIS - Current Research Information System)
Subject Terms: artificial intelligence, computer hardware, computer network, computer programming, computer science, computer system, distributed computer system, distributed system, embedded system, engineering, internet, machine learning, microprocessor chip, parallel processing system, processor, signal processing
Description: An open challenge in making Internet-of-Things sensor nodes "smart'' and self-adaptive is to enable on-chip Deep Neural Network (DNN) training on Ultra-Low-Power (ULP) microcontroller units (MCUs). To this aim, we present a framework, based on PULP-TrainLib, to deploy DNN training tasks on RISC-V-based Parallel-ULP (PULP) MCUs. PULP-TrainLib is a library of parallel software DNN primitives enabling the execution of forward and backward steps on PULP MCUs. To optimize PULP-TrainLib's kernels, we propose a strategy to automatically select and configure (autotune) the fastest among a set of tiling options and optimized floating-point matrix multiplication kernels, according to the tensor shapes of every DNN layer. Results on an 8-core RISC-V MCU show that our auto-tuned primitives improve MAC/clk by up to 2.4x compared to "one-size-fits-all'' matrix multiplication, achieving up to 4.39 MAC/clk - 36.6x better than a commercial STM32L4 MCU executing the same DNN layer training workload. Furthermore, our strategy proves to be 30.7x faster than AIfES, a state-of-the-art training library for MCUs, while training a complete TinyML model.
Document Type: conference object
File Description: STAMPA
Language: English
Relation: info:eu-repo/semantics/altIdentifier/isbn/978-3-031-15073-9; info:eu-repo/semantics/altIdentifier/isbn/978-3-031-15074-6; info:eu-repo/semantics/altIdentifier/wos/WOS:000874744300013; ispartofbook:Embedded Computer Systems: Architectures, Modeling, and Simulation; 22nd International Conference, SAMOS 2022; volume:13511; firstpage:200; lastpage:216; numberofpages:17; info:eu-repo/grantAgreement/EC/H2020/826060, 863337; https://hdl.handle.net/11585/900686
DOI: 10.1007/978-3-031-15074-6_13
Availability: https://hdl.handle.net/11585/900686
https://doi.org/10.1007/978-3-031-15074-6_13
https://link.springer.com/chapter/10.1007/978-3-031-15074-6_13
Rights: info:eu-repo/semantics/openAccess
Accession Number: edsbas.BF3FAEEB
Database: BASE
FullText Text:
  Availability: 0
CustomLinks:
  – Url: https://hdl.handle.net/11585/900686#
    Name: EDS - BASE (ns324271)
    Category: fullText
    Text: View record from BASE
Header DbId: edsbas
DbLabel: BASE
An: edsbas.BF3FAEEB
RelevancyScore: 935
AccessLevel: 3
PubType: Conference
PubTypeId: conference
PreciseRelevancyScore: 935.2763671875
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Nadalini+D%2E%22">Nadalini D.</searchLink><br /><searchLink fieldCode="AR" term="%22Rusci+M%2E%22">Rusci M.</searchLink><br /><searchLink fieldCode="AR" term="%22Tagliavini+G%2E%22">Tagliavini G.</searchLink><br /><searchLink fieldCode="AR" term="%22Ravaglia+L%2E%22">Ravaglia L.</searchLink><br /><searchLink fieldCode="AR" term="%22Benini+L%2E%22">Benini L.</searchLink><br /><searchLink fieldCode="AR" term="%22Conti+F%2E%22">Conti F.</searchLink>
– Name: Author
  Label: Contributors
  Group: Au
  Data: Nadalini D.<br />Rusci M.<br />Tagliavini G.<br />Ravaglia L.<br />Benini L.<br />Conti F.
– Name: Publisher
  Label: Publisher Information
  Group: PubInfo
  Data: Springer
– Name: DatePubCY
  Label: Publication Year
  Group: Date
  Data: 2022
– Name: Subset
  Label: Collection
  Group: HoldingsInfo
  Data: IRIS Università degli Studi di Bologna (CRIS - Current Research Information System)
– Name: Subject
  Label: Subject Terms
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22artificial+intelligence%22">artificial intelligence</searchLink><br /><searchLink fieldCode="DE" term="%22computer+hardware%22">computer hardware</searchLink><br /><searchLink fieldCode="DE" term="%22computer+network%22">computer network</searchLink><br /><searchLink fieldCode="DE" term="%22computer+programming%22">computer programming</searchLink><br /><searchLink fieldCode="DE" term="%22computer+science%22">computer science</searchLink><br /><searchLink fieldCode="DE" term="%22computer+system%22">computer system</searchLink><br /><searchLink fieldCode="DE" term="%22distributed+computer+system%22">distributed computer system</searchLink><br /><searchLink fieldCode="DE" term="%22distributed+system%22">distributed system</searchLink><br /><searchLink fieldCode="DE" term="%22embedded+system%22">embedded system</searchLink><br /><searchLink fieldCode="DE" term="%22engineering%22">engineering</searchLink><br /><searchLink fieldCode="DE" term="%22internet%22">internet</searchLink><br /><searchLink fieldCode="DE" term="%22machine+learning%22">machine learning</searchLink><br /><searchLink fieldCode="DE" term="%22microprocessor+chip%22">microprocessor chip</searchLink><br /><searchLink fieldCode="DE" term="%22parallel+processing+system%22">parallel processing system</searchLink><br /><searchLink fieldCode="DE" term="%22processor%22">processor</searchLink><br /><searchLink fieldCode="DE" term="%22signal+processing%22">signal processing</searchLink>
– Name: Abstract
  Label: Description
  Group: Ab
  Data: An open challenge in making Internet-of-Things sensor nodes "smart'' and self-adaptive is to enable on-chip Deep Neural Network (DNN) training on Ultra-Low-Power (ULP) microcontroller units (MCUs). To this aim, we present a framework, based on PULP-TrainLib, to deploy DNN training tasks on RISC-V-based Parallel-ULP (PULP) MCUs. PULP-TrainLib is a library of parallel software DNN primitives enabling the execution of forward and backward steps on PULP MCUs. To optimize PULP-TrainLib's kernels, we propose a strategy to automatically select and configure (autotune) the fastest among a set of tiling options and optimized floating-point matrix multiplication kernels, according to the tensor shapes of every DNN layer. Results on an 8-core RISC-V MCU show that our auto-tuned primitives improve MAC/clk by up to 2.4x compared to "one-size-fits-all'' matrix multiplication, achieving up to 4.39 MAC/clk - 36.6x better than a commercial STM32L4 MCU executing the same DNN layer training workload. Furthermore, our strategy proves to be 30.7x faster than AIfES, a state-of-the-art training library for MCUs, while training a complete TinyML model.
– Name: TypeDocument
  Label: Document Type
  Group: TypDoc
  Data: conference object
– Name: Format
  Label: File Description
  Group: SrcInfo
  Data: STAMPA
– Name: Language
  Label: Language
  Group: Lang
  Data: English
– Name: NoteTitleSource
  Label: Relation
  Group: SrcInfo
  Data: info:eu-repo/semantics/altIdentifier/isbn/978-3-031-15073-9; info:eu-repo/semantics/altIdentifier/isbn/978-3-031-15074-6; info:eu-repo/semantics/altIdentifier/wos/WOS:000874744300013; ispartofbook:Embedded Computer Systems: Architectures, Modeling, and Simulation; 22nd International Conference, SAMOS 2022; volume:13511; firstpage:200; lastpage:216; numberofpages:17; info:eu-repo/grantAgreement/EC/H2020/826060, 863337; https://hdl.handle.net/11585/900686
– Name: DOI
  Label: DOI
  Group: ID
  Data: 10.1007/978-3-031-15074-6_13
– Name: URL
  Label: Availability
  Group: URL
  Data: https://hdl.handle.net/11585/900686<br />https://doi.org/10.1007/978-3-031-15074-6_13<br />https://link.springer.com/chapter/10.1007/978-3-031-15074-6_13
– Name: Copyright
  Label: Rights
  Group: Cpyrght
  Data: info:eu-repo/semantics/openAccess
– Name: AN
  Label: Accession Number
  Group: ID
  Data: edsbas.BF3FAEEB
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edsbas&AN=edsbas.BF3FAEEB
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1007/978-3-031-15074-6_13
    Languages:
      – Text: English
    Subjects:
      – SubjectFull: artificial intelligence
        Type: general
      – SubjectFull: computer hardware
        Type: general
      – SubjectFull: computer network
        Type: general
      – SubjectFull: computer programming
        Type: general
      – SubjectFull: computer science
        Type: general
      – SubjectFull: computer system
        Type: general
      – SubjectFull: distributed computer system
        Type: general
      – SubjectFull: distributed system
        Type: general
      – SubjectFull: embedded system
        Type: general
      – SubjectFull: engineering
        Type: general
      – SubjectFull: internet
        Type: general
      – SubjectFull: machine learning
        Type: general
      – SubjectFull: microprocessor chip
        Type: general
      – SubjectFull: parallel processing system
        Type: general
      – SubjectFull: processor
        Type: general
      – SubjectFull: signal processing
        Type: general
    Titles:
      – TitleFull: PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Nadalini D.
      – PersonEntity:
          Name:
            NameFull: Rusci M.
      – PersonEntity:
          Name:
            NameFull: Tagliavini G.
      – PersonEntity:
          Name:
            NameFull: Ravaglia L.
      – PersonEntity:
          Name:
            NameFull: Benini L.
      – PersonEntity:
          Name:
            NameFull: Conti F.
      – PersonEntity:
          Name:
            NameFull: Nadalini D.
      – PersonEntity:
          Name:
            NameFull: Rusci M.
      – PersonEntity:
          Name:
            NameFull: Tagliavini G.
      – PersonEntity:
          Name:
            NameFull: Ravaglia L.
      – PersonEntity:
          Name:
            NameFull: Benini L.
      – PersonEntity:
          Name:
            NameFull: Conti F.
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 01
              Type: published
              Y: 2022
          Identifiers:
            – Type: issn-locals
              Value: edsbas
            – Type: issn-locals
              Value: edsbas.oa
ResultId 1