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Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys

Λεπτομέρειες βιβλιογραφικής εγγραφής
Τίτλος: Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys
Συγγραφείς: Araújo, Sílvio Roberto Fernandes de
Συνεισφορές: Silva, Ivan Saraiva, http://lattes.cnpq.br/5111916887378777, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2, Susin, Altamiro Amadeu, http://lattes.cnpq.br/6766389440522985, Zeferino, Cesar Albenes, http://lattes.cnpq.br/9888386354516064, Déharbe, David Boris Paul, http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4768856U5, Kreutz, Márcio Eduardo, http://lattes.cnpq.br/6374279398246756
Στοιχεία εκδότη: Universidade Federal do Rio Grande do Norte
BR
UFRN
Programa de Pós-Graduação em Sistemas e Computação
Ciência da Computação
Έτος έκδοσης: 2014
Συλλογή: Universidade Federal do Rio Grande do Norte: Repositório Institucional (RI UFRN)
Θεματικοί όροι: Multiprocessador em chip, MPSoC, Redes em chip, NoC, Algoritmo spiral complement, Sistema IPNoSys, Multiprocessor on chip, Network-on-chip, Spiral complement algorithm, IPNoSys system, CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
Περιγραφή: It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it ...
Τύπος εγγράφου: doctoral or postdoctoral thesis
Περιγραφή αρχείου: application/pdf
Γλώσσα: Portuguese
Relation: https://repositorio.ufrn.br/jspui/handle/123456789/17948
Διαθεσιμότητα: https://repositorio.ufrn.br/jspui/handle/123456789/17948
Rights: Acesso Aberto
Αριθμός Καταχώρησης: edsbas.8A9FAF2A
Βάση Δεδομένων: BASE
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PubType: Dissertation/ Thesis
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  Data: Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys
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  Data: Silva, Ivan Saraiva<br />http://lattes.cnpq.br/5111916887378777<br />http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4780113E2<br />Susin, Altamiro Amadeu<br />http://lattes.cnpq.br/6766389440522985<br />Zeferino, Cesar Albenes<br />http://lattes.cnpq.br/9888386354516064<br />Déharbe, David Boris Paul<br />http://buscatextual.cnpq.br/buscatextual/visualizacv.do?id=K4768856U5<br />Kreutz, Márcio Eduardo<br />http://lattes.cnpq.br/6374279398246756
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  Data: Universidade Federal do Rio Grande do Norte<br />BR<br />UFRN<br />Programa de Pós-Graduação em Sistemas e Computação<br />Ciência da Computação
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  Data: 2014
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  Data: Universidade Federal do Rio Grande do Norte: Repositório Institucional (RI UFRN)
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  Data: <searchLink fieldCode="DE" term="%22Multiprocessador+em+chip%22">Multiprocessador em chip</searchLink><br /><searchLink fieldCode="DE" term="%22MPSoC%22">MPSoC</searchLink><br /><searchLink fieldCode="DE" term="%22Redes+em+chip%22">Redes em chip</searchLink><br /><searchLink fieldCode="DE" term="%22NoC%22">NoC</searchLink><br /><searchLink fieldCode="DE" term="%22Algoritmo+spiral+complement%22">Algoritmo spiral complement</searchLink><br /><searchLink fieldCode="DE" term="%22Sistema+IPNoSys%22">Sistema IPNoSys</searchLink><br /><searchLink fieldCode="DE" term="%22Multiprocessor+on+chip%22">Multiprocessor on chip</searchLink><br /><searchLink fieldCode="DE" term="%22Network-on-chip%22">Network-on-chip</searchLink><br /><searchLink fieldCode="DE" term="%22Spiral+complement+algorithm%22">Spiral complement algorithm</searchLink><br /><searchLink fieldCode="DE" term="%22IPNoSys+system%22">IPNoSys system</searchLink><br /><searchLink fieldCode="DE" term="%22CNPQ%3A%3ACIENCIAS+EXATAS+E+DA+TERRA%3A%3ACIENCIA+DA+COMPUTACAO%3A%3ASISTEMAS+DE+COMPUTACAO%22">CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO</searchLink>
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  Data: It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it ...
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RecordInfo BibRecord:
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    Languages:
      – Text: Portuguese
    Subjects:
      – SubjectFull: Multiprocessador em chip
        Type: general
      – SubjectFull: MPSoC
        Type: general
      – SubjectFull: Redes em chip
        Type: general
      – SubjectFull: NoC
        Type: general
      – SubjectFull: Algoritmo spiral complement
        Type: general
      – SubjectFull: Sistema IPNoSys
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      – SubjectFull: Multiprocessor on chip
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      – SubjectFull: Spiral complement algorithm
        Type: general
      – SubjectFull: IPNoSys system
        Type: general
      – SubjectFull: CNPQ::CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::SISTEMAS DE COMPUTACAO
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      – TitleFull: Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys
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