Bibliographic Details
| Title: |
A novel high-K SONOS type non-volatile memory and NMOS HfO₂ Vth instability studies for gate electrode and interface threatment effects |
| Authors: |
Wang, Xuguang |
| Contributors: |
Kwong, Dim-Lee |
| Publication Year: |
2005 |
| Collection: |
The University of Texas at Austin: Texas ScholarWorks |
| Subject Terms: |
Computer engineering--Data processing, Scanning tunneling microscopy, Metal oxide semiconductors |
| Description: |
text ; According to the 2004 International Technology Roadmaps for Semiconductors (ITRS), one of the most important challenges in the semiconductor flash memory industry is the continuously scaling of the tunneling oxide thickness. As the tunneling oxide is thinner than 100Å, it becomes a formidable challenge to obtain a fast programming and a 10-year long retention simultaneously. In this work, novel Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type non-volatile memories using high-K dielectric materials are proposed to tackle this problem. Thanks to its lower carrier injection barrier, HfO2 is found beneficial to improve the programming efficiency even with a physically thicker tunneling oxide as compared to equivalent SiO2. This thicker tunneling oxide together with a much deeper trap level of the Ta2O5 ensures a better retention as compared to thinner SiO2 tunneling layer and the Si3N4 trapping layer. Therefore, a better trade-off between the faster programming and longer retention is obtained in such high-K SONOS memories. Two structures, the TaN-HfO2-Ta2O5-HfO2-Si (MHTHS) and the TaN-Al2O3-Ta2O5-HfO2-Si (MATHS) are compared and MATHS is found to have better charge blocking due to the higher barrier of Al2O3 as the top oxide. The fabricated devices demonstrate fast programming, excellent retention, endurance, and read disturbance as compared to state-of-the-art SONOS devices. The impacts of the top gate electrodes and bottom interface treatments on the NMOS HfO2 Vth instability are also studied. This knowledge is very important not only to the memory but also to the logic device applications. Both DC and AC stresses are used. The O3 treated interface is found to lead to worse Vth instability due to the enhanced valance band electrons injection as compared to NH3 treated interface. While a top interfacial layer formed in the poly-Si gated samples is found to introduce more charges trapping under DC stresses than the TiN metal gated samples. But this top layer only plays a minor effect once the stress ... |
| Document Type: |
thesis |
| File Description: |
electronic; application/pdf |
| Language: |
English |
| Relation: |
b60824098; http://hdl.handle.net/2152/2089 |
| Availability: |
http://hdl.handle.net/2152/2089 |
| Rights: |
Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works. |
| Accession Number: |
edsbas.8531E7D6 |
| Database: |
BASE |